-- Copyright (C) 1991-2013 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II 64-Bit"
-- VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Full Version"

-- DATE "04/10/2021 22:41:28"

-- 
-- Device: Altera EP3C40F780C8 Package FBGA780
-- 

-- 
-- This VHDL file should be used for ModelSim-Altera (VHDL) only
-- 

LIBRARY ALTERA;
LIBRARY CYCLONEIII;
LIBRARY IEEE;
USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
USE CYCLONEIII.CYCLONEIII_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY 	zl_2346_pre2 IS
    PORT (
	clr : IN std_logic;
	clk : IN std_logic;
	set : IN std_logic;
	datain : IN std_logic_vector(15 DOWNTO 0);
	en : OUT std_logic_vector(3 DOWNTO 0);
	codeout : OUT std_logic_vector(7 DOWNTO 0)
	);
END zl_2346_pre2;

-- Design Ports Information
-- en[0]	=>  Location: PIN_F17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- en[1]	=>  Location: PIN_H15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- en[2]	=>  Location: PIN_C19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- en[3]	=>  Location: PIN_G18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[0]	=>  Location: PIN_H14,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[1]	=>  Location: PIN_K15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[2]	=>  Location: PIN_D16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[3]	=>  Location: PIN_E15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[4]	=>  Location: PIN_B17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[5]	=>  Location: PIN_C15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[6]	=>  Location: PIN_A17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- codeout[7]	=>  Location: PIN_D21,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clk	=>  Location: PIN_J2,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[12]	=>  Location: PIN_G15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- clr	=>  Location: PIN_A19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- set	=>  Location: PIN_G17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[13]	=>  Location: PIN_C17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[14]	=>  Location: PIN_H16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[15]	=>  Location: PIN_J17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[8]	=>  Location: PIN_A18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[9]	=>  Location: PIN_B19,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[10]	=>  Location: PIN_D18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[11]	=>  Location: PIN_E17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[4]	=>  Location: PIN_F15,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[5]	=>  Location: PIN_D17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[6]	=>  Location: PIN_B18,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[7]	=>  Location: PIN_H17,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[0]	=>  Location: PIN_J16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[1]	=>  Location: PIN_C16,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[2]	=>  Location: PIN_D20,	 I/O Standard: 2.5 V,	 Current Strength: Default
-- datain[3]	=>  Location: PIN_G16,	 I/O Standard: 2.5 V,	 Current Strength: Default


ARCHITECTURE structure OF zl_2346_pre2 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL unknown : std_logic := 'X';
SIGNAL devoe : std_logic := '1';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_clr : std_logic;
SIGNAL ww_clk : std_logic;
SIGNAL ww_set : std_logic;
SIGNAL ww_datain : std_logic_vector(15 DOWNTO 0);
SIGNAL ww_en : std_logic_vector(3 DOWNTO 0);
SIGNAL ww_codeout : std_logic_vector(7 DOWNTO 0);
SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
SIGNAL \en[0]~output_o\ : std_logic;
SIGNAL \en[1]~output_o\ : std_logic;
SIGNAL \en[2]~output_o\ : std_logic;
SIGNAL \en[3]~output_o\ : std_logic;
SIGNAL \codeout[0]~output_o\ : std_logic;
SIGNAL \codeout[1]~output_o\ : std_logic;
SIGNAL \codeout[2]~output_o\ : std_logic;
SIGNAL \codeout[3]~output_o\ : std_logic;
SIGNAL \codeout[4]~output_o\ : std_logic;
SIGNAL \codeout[5]~output_o\ : std_logic;
SIGNAL \codeout[6]~output_o\ : std_logic;
SIGNAL \codeout[7]~output_o\ : std_logic;
SIGNAL \clk~input_o\ : std_logic;
SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
SIGNAL \clr~input_o\ : std_logic;
SIGNAL \datain[10]~input_o\ : std_logic;
SIGNAL \B~7_combout\ : std_logic;
SIGNAL \set~input_o\ : std_logic;
SIGNAL \B[2]~1_combout\ : std_logic;
SIGNAL \datain[8]~input_o\ : std_logic;
SIGNAL \B~5_combout\ : std_logic;
SIGNAL \datain[9]~input_o\ : std_logic;
SIGNAL \B~6_combout\ : std_logic;
SIGNAL \datain[11]~input_o\ : std_logic;
SIGNAL \B~8_combout\ : std_logic;
SIGNAL \B[11]~feeder_combout\ : std_logic;
SIGNAL \always2~1_combout\ : std_logic;
SIGNAL \datain[12]~input_o\ : std_logic;
SIGNAL \B~0_combout\ : std_logic;
SIGNAL \datain[13]~input_o\ : std_logic;
SIGNAL \B~2_combout\ : std_logic;
SIGNAL \datain[15]~input_o\ : std_logic;
SIGNAL \B~4_combout\ : std_logic;
SIGNAL \datain[14]~input_o\ : std_logic;
SIGNAL \B~3_combout\ : std_logic;
SIGNAL \always2~0_combout\ : std_logic;
SIGNAL \Add0~0_combout\ : std_logic;
SIGNAL \Add0~1\ : std_logic;
SIGNAL \Add0~2_combout\ : std_logic;
SIGNAL \Add0~3\ : std_logic;
SIGNAL \Add0~4_combout\ : std_logic;
SIGNAL \Add0~5\ : std_logic;
SIGNAL \Add0~6_combout\ : std_logic;
SIGNAL \Add0~7\ : std_logic;
SIGNAL \Add0~8_combout\ : std_logic;
SIGNAL \Add0~15\ : std_logic;
SIGNAL \Add0~16_combout\ : std_logic;
SIGNAL \time_count~1_combout\ : std_logic;
SIGNAL \Add0~17\ : std_logic;
SIGNAL \Add0~18_combout\ : std_logic;
SIGNAL \Add0~19\ : std_logic;
SIGNAL \Add0~20_combout\ : std_logic;
SIGNAL \Add0~21\ : std_logic;
SIGNAL \Add0~22_combout\ : std_logic;
SIGNAL \Add0~23\ : std_logic;
SIGNAL \Add0~24_combout\ : std_logic;
SIGNAL \Add0~25\ : std_logic;
SIGNAL \Add0~26_combout\ : std_logic;
SIGNAL \Add0~27\ : std_logic;
SIGNAL \Add0~28_combout\ : std_logic;
SIGNAL \Add0~29\ : std_logic;
SIGNAL \Add0~30_combout\ : std_logic;
SIGNAL \Equal0~0_combout\ : std_logic;
SIGNAL \Equal0~1_combout\ : std_logic;
SIGNAL \Equal0~2_combout\ : std_logic;
SIGNAL \Equal0~3_combout\ : std_logic;
SIGNAL \Equal0~4_combout\ : std_logic;
SIGNAL \time_count~2_combout\ : std_logic;
SIGNAL \Add0~9\ : std_logic;
SIGNAL \Add0~10_combout\ : std_logic;
SIGNAL \Add0~11\ : std_logic;
SIGNAL \Add0~12_combout\ : std_logic;
SIGNAL \Add0~13\ : std_logic;
SIGNAL \Add0~14_combout\ : std_logic;
SIGNAL \time_count~0_combout\ : std_logic;
SIGNAL \LessThan1~0_combout\ : std_logic;
SIGNAL \LessThan2~0_combout\ : std_logic;
SIGNAL \LessThan2~1_combout\ : std_logic;
SIGNAL \LessThan1~1_combout\ : std_logic;
SIGNAL \always2~8_combout\ : std_logic;
SIGNAL \always2~5_combout\ : std_logic;
SIGNAL \always2~6_combout\ : std_logic;
SIGNAL \always2~7_combout\ : std_logic;
SIGNAL \LessThan2~3_combout\ : std_logic;
SIGNAL \datain[5]~input_o\ : std_logic;
SIGNAL \B~10_combout\ : std_logic;
SIGNAL \datain[6]~input_o\ : std_logic;
SIGNAL \B~11_combout\ : std_logic;
SIGNAL \datain[7]~input_o\ : std_logic;
SIGNAL \B~12_combout\ : std_logic;
SIGNAL \datain[4]~input_o\ : std_logic;
SIGNAL \B~9_combout\ : std_logic;
SIGNAL \always2~2_combout\ : std_logic;
SIGNAL \always2~3_combout\ : std_logic;
SIGNAL \LessThan2~2_combout\ : std_logic;
SIGNAL \always2~4_combout\ : std_logic;
SIGNAL \en~0_combout\ : std_logic;
SIGNAL \en[0]~reg0_q\ : std_logic;
SIGNAL \en[1]~1_combout\ : std_logic;
SIGNAL \en~2_combout\ : std_logic;
SIGNAL \en[1]~reg0_q\ : std_logic;
SIGNAL \en~3_combout\ : std_logic;
SIGNAL \en[2]~reg0_q\ : std_logic;
SIGNAL \en[3]~reg0_q\ : std_logic;
SIGNAL \datain[1]~input_o\ : std_logic;
SIGNAL \B~14_combout\ : std_logic;
SIGNAL \data[3]~0_combout\ : std_logic;
SIGNAL \data~3_combout\ : std_logic;
SIGNAL \data~4_combout\ : std_logic;
SIGNAL \datain[0]~input_o\ : std_logic;
SIGNAL \B~13_combout\ : std_logic;
SIGNAL \data~1_combout\ : std_logic;
SIGNAL \data~2_combout\ : std_logic;
SIGNAL \datain[3]~input_o\ : std_logic;
SIGNAL \B~16_combout\ : std_logic;
SIGNAL \data~7_combout\ : std_logic;
SIGNAL \data~8_combout\ : std_logic;
SIGNAL \datain[2]~input_o\ : std_logic;
SIGNAL \B~15_combout\ : std_logic;
SIGNAL \data~5_combout\ : std_logic;
SIGNAL \data~6_combout\ : std_logic;
SIGNAL \WideOr6~0_combout\ : std_logic;
SIGNAL \WideOr5~0_combout\ : std_logic;
SIGNAL \WideOr4~0_combout\ : std_logic;
SIGNAL \WideOr3~0_combout\ : std_logic;
SIGNAL \WideOr2~0_combout\ : std_logic;
SIGNAL \WideOr1~0_combout\ : std_logic;
SIGNAL \WideOr0~0_combout\ : std_logic;
SIGNAL time_count : std_logic_vector(15 DOWNTO 0);
SIGNAL data : std_logic_vector(3 DOWNTO 0);
SIGNAL B : std_logic_vector(15 DOWNTO 0);
SIGNAL \ALT_INV_WideOr1~0_combout\ : std_logic;
SIGNAL \ALT_INV_WideOr2~0_combout\ : std_logic;
SIGNAL \ALT_INV_WideOr3~0_combout\ : std_logic;
SIGNAL \ALT_INV_WideOr4~0_combout\ : std_logic;
SIGNAL \ALT_INV_WideOr5~0_combout\ : std_logic;
SIGNAL \ALT_INV_WideOr6~0_combout\ : std_logic;

BEGIN

ww_clr <= clr;
ww_clk <= clk;
ww_set <= set;
ww_datain <= datain;
en <= ww_en;
codeout <= ww_codeout;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;

\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
\ALT_INV_WideOr1~0_combout\ <= NOT \WideOr1~0_combout\;
\ALT_INV_WideOr2~0_combout\ <= NOT \WideOr2~0_combout\;
\ALT_INV_WideOr3~0_combout\ <= NOT \WideOr3~0_combout\;
\ALT_INV_WideOr4~0_combout\ <= NOT \WideOr4~0_combout\;
\ALT_INV_WideOr5~0_combout\ <= NOT \WideOr5~0_combout\;
\ALT_INV_WideOr6~0_combout\ <= NOT \WideOr6~0_combout\;

-- Location: IOOBUF_X48_Y43_N30
\en[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \en[0]~reg0_q\,
	devoe => ww_devoe,
	o => \en[0]~output_o\);

-- Location: IOOBUF_X48_Y43_N23
\en[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \en[1]~reg0_q\,
	devoe => ww_devoe,
	o => \en[1]~output_o\);

-- Location: IOOBUF_X48_Y43_N2
\en[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \en[2]~reg0_q\,
	devoe => ww_devoe,
	o => \en[2]~output_o\);

-- Location: IOOBUF_X48_Y43_N16
\en[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \en[3]~reg0_q\,
	devoe => ww_devoe,
	o => \en[3]~output_o\);

-- Location: IOOBUF_X38_Y43_N9
\codeout[0]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr6~0_combout\,
	devoe => ww_devoe,
	o => \codeout[0]~output_o\);

-- Location: IOOBUF_X38_Y43_N16
\codeout[1]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr5~0_combout\,
	devoe => ww_devoe,
	o => \codeout[1]~output_o\);

-- Location: IOOBUF_X38_Y43_N2
\codeout[2]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr4~0_combout\,
	devoe => ww_devoe,
	o => \codeout[2]~output_o\);

-- Location: IOOBUF_X36_Y43_N2
\codeout[3]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr3~0_combout\,
	devoe => ww_devoe,
	o => \codeout[3]~output_o\);

-- Location: IOOBUF_X38_Y43_N30
\codeout[4]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr2~0_combout\,
	devoe => ww_devoe,
	o => \codeout[4]~output_o\);

-- Location: IOOBUF_X36_Y43_N16
\codeout[5]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \ALT_INV_WideOr1~0_combout\,
	devoe => ww_devoe,
	o => \codeout[5]~output_o\);

-- Location: IOOBUF_X38_Y43_N23
\codeout[6]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => \WideOr0~0_combout\,
	devoe => ww_devoe,
	o => \codeout[6]~output_o\);

-- Location: IOOBUF_X54_Y43_N2
\codeout[7]~output\ : cycloneiii_io_obuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	open_drain_output => "false")
-- pragma translate_on
PORT MAP (
	i => GND,
	devoe => ww_devoe,
	o => \codeout[7]~output_o\);

-- Location: IOIBUF_X0_Y21_N1
\clk~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clk,
	o => \clk~input_o\);

-- Location: CLKCTRL_G4
\clk~inputclkctrl\ : cycloneiii_clkctrl
-- pragma translate_off
GENERIC MAP (
	clock_type => "global clock",
	ena_register_mode => "none")
-- pragma translate_on
PORT MAP (
	inclk => \clk~inputclkctrl_INCLK_bus\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	outclk => \clk~inputclkctrl_outclk\);

-- Location: IOIBUF_X45_Y43_N8
\clr~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_clr,
	o => \clr~input_o\);

-- Location: IOIBUF_X50_Y43_N1
\datain[10]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(10),
	o => \datain[10]~input_o\);

-- Location: LCCOMB_X45_Y42_N30
\B~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~7_combout\ = (!\clr~input_o\ & \datain[10]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[10]~input_o\,
	combout => \B~7_combout\);

-- Location: IOIBUF_X50_Y43_N22
\set~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_set,
	o => \set~input_o\);

-- Location: LCCOMB_X45_Y42_N24
\B[2]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B[2]~1_combout\ = (\clr~input_o\) # (\set~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \set~input_o\,
	combout => \B[2]~1_combout\);

-- Location: FF_X45_Y42_N31
\B[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~7_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(10));

-- Location: IOIBUF_X45_Y43_N22
\datain[8]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(8),
	o => \datain[8]~input_o\);

-- Location: LCCOMB_X45_Y42_N18
\B~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~5_combout\ = (!\clr~input_o\ & \datain[8]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[8]~input_o\,
	combout => \B~5_combout\);

-- Location: FF_X45_Y42_N19
\B[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~5_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(8));

-- Location: IOIBUF_X45_Y43_N15
\datain[9]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(9),
	o => \datain[9]~input_o\);

-- Location: LCCOMB_X45_Y42_N4
\B~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~6_combout\ = (!\clr~input_o\ & \datain[9]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[9]~input_o\,
	combout => \B~6_combout\);

-- Location: FF_X45_Y42_N5
\B[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~6_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(9));

-- Location: IOIBUF_X43_Y43_N1
\datain[11]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(11),
	o => \datain[11]~input_o\);

-- Location: LCCOMB_X44_Y42_N24
\B~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~8_combout\ = (!\clr~input_o\ & \datain[11]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[11]~input_o\,
	combout => \B~8_combout\);

-- Location: LCCOMB_X45_Y42_N16
\B[11]~feeder\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B[11]~feeder_combout\ = \B~8_combout\

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datad => \B~8_combout\,
	combout => \B[11]~feeder_combout\);

-- Location: FF_X45_Y42_N17
\B[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B[11]~feeder_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(11));

-- Location: LCCOMB_X45_Y42_N10
\always2~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~1_combout\ = (!B(10) & (!B(8) & (!B(9) & !B(11))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(10),
	datab => B(8),
	datac => B(9),
	datad => B(11),
	combout => \always2~1_combout\);

-- Location: IOIBUF_X41_Y43_N8
\datain[12]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(12),
	o => \datain[12]~input_o\);

-- Location: LCCOMB_X44_Y42_N10
\B~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~0_combout\ = (!\clr~input_o\ & \datain[12]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101010100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datad => \datain[12]~input_o\,
	combout => \B~0_combout\);

-- Location: FF_X44_Y42_N11
\B[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~0_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(12));

-- Location: IOIBUF_X48_Y43_N8
\datain[13]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(13),
	o => \datain[13]~input_o\);

-- Location: LCCOMB_X44_Y42_N4
\B~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~2_combout\ = (!\clr~input_o\ & \datain[13]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[13]~input_o\,
	combout => \B~2_combout\);

-- Location: FF_X44_Y42_N5
\B[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~2_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(13));

-- Location: IOIBUF_X43_Y43_N15
\datain[15]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(15),
	o => \datain[15]~input_o\);

-- Location: LCCOMB_X44_Y42_N8
\B~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~4_combout\ = (!\clr~input_o\ & \datain[15]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[15]~input_o\,
	combout => \B~4_combout\);

-- Location: FF_X44_Y42_N9
\B[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~4_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(15));

-- Location: IOIBUF_X43_Y43_N22
\datain[14]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(14),
	o => \datain[14]~input_o\);

-- Location: LCCOMB_X44_Y42_N18
\B~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~3_combout\ = (!\clr~input_o\ & \datain[14]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[14]~input_o\,
	combout => \B~3_combout\);

-- Location: FF_X44_Y42_N19
\B[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~3_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(14));

-- Location: LCCOMB_X44_Y42_N6
\always2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~0_combout\ = (!B(12) & (!B(13) & (!B(15) & !B(14))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(12),
	datab => B(13),
	datac => B(15),
	datad => B(14),
	combout => \always2~0_combout\);

-- Location: LCCOMB_X49_Y42_N0
\Add0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~0_combout\ = time_count(0) $ (VCC)
-- \Add0~1\ = CARRY(time_count(0))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001111001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => time_count(0),
	datad => VCC,
	combout => \Add0~0_combout\,
	cout => \Add0~1\);

-- Location: FF_X49_Y42_N1
\time_count[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(0));

-- Location: LCCOMB_X49_Y42_N2
\Add0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~2_combout\ = (time_count(1) & (!\Add0~1\)) # (!time_count(1) & ((\Add0~1\) # (GND)))
-- \Add0~3\ = CARRY((!\Add0~1\) # (!time_count(1)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(1),
	datad => VCC,
	cin => \Add0~1\,
	combout => \Add0~2_combout\,
	cout => \Add0~3\);

-- Location: FF_X49_Y42_N3
\time_count[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(1));

-- Location: LCCOMB_X49_Y42_N4
\Add0~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~4_combout\ = (time_count(2) & (\Add0~3\ $ (GND))) # (!time_count(2) & (!\Add0~3\ & VCC))
-- \Add0~5\ = CARRY((time_count(2) & !\Add0~3\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(2),
	datad => VCC,
	cin => \Add0~3\,
	combout => \Add0~4_combout\,
	cout => \Add0~5\);

-- Location: FF_X49_Y42_N5
\time_count[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(2));

-- Location: LCCOMB_X49_Y42_N6
\Add0~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~6_combout\ = (time_count(3) & (!\Add0~5\)) # (!time_count(3) & ((\Add0~5\) # (GND)))
-- \Add0~7\ = CARRY((!\Add0~5\) # (!time_count(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(3),
	datad => VCC,
	cin => \Add0~5\,
	combout => \Add0~6_combout\,
	cout => \Add0~7\);

-- Location: FF_X49_Y42_N7
\time_count[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(3));

-- Location: LCCOMB_X49_Y42_N8
\Add0~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~8_combout\ = (time_count(4) & (\Add0~7\ $ (GND))) # (!time_count(4) & (!\Add0~7\ & VCC))
-- \Add0~9\ = CARRY((time_count(4) & !\Add0~7\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(4),
	datad => VCC,
	cin => \Add0~7\,
	combout => \Add0~8_combout\,
	cout => \Add0~9\);

-- Location: FF_X49_Y42_N27
\time_count[13]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~26_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(13));

-- Location: LCCOMB_X49_Y42_N14
\Add0~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~14_combout\ = (time_count(7) & (!\Add0~13\)) # (!time_count(7) & ((\Add0~13\) # (GND)))
-- \Add0~15\ = CARRY((!\Add0~13\) # (!time_count(7)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(7),
	datad => VCC,
	cin => \Add0~13\,
	combout => \Add0~14_combout\,
	cout => \Add0~15\);

-- Location: LCCOMB_X49_Y42_N16
\Add0~16\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~16_combout\ = (time_count(8) & (\Add0~15\ $ (GND))) # (!time_count(8) & (!\Add0~15\ & VCC))
-- \Add0~17\ = CARRY((time_count(8) & !\Add0~15\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(8),
	datad => VCC,
	cin => \Add0~15\,
	combout => \Add0~16_combout\,
	cout => \Add0~17\);

-- Location: LCCOMB_X50_Y42_N22
\time_count~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \time_count~1_combout\ = (\Add0~16_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \Add0~16_combout\,
	datad => \Equal0~4_combout\,
	combout => \time_count~1_combout\);

-- Location: FF_X50_Y42_N23
\time_count[8]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \time_count~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(8));

-- Location: LCCOMB_X49_Y42_N18
\Add0~18\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~18_combout\ = (time_count(9) & (!\Add0~17\)) # (!time_count(9) & ((\Add0~17\) # (GND)))
-- \Add0~19\ = CARRY((!\Add0~17\) # (!time_count(9)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011110000111111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(9),
	datad => VCC,
	cin => \Add0~17\,
	combout => \Add0~18_combout\,
	cout => \Add0~19\);

-- Location: FF_X49_Y42_N19
\time_count[9]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~18_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(9));

-- Location: LCCOMB_X49_Y42_N20
\Add0~20\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~20_combout\ = (time_count(10) & (\Add0~19\ $ (GND))) # (!time_count(10) & (!\Add0~19\ & VCC))
-- \Add0~21\ = CARRY((time_count(10) & !\Add0~19\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(10),
	datad => VCC,
	cin => \Add0~19\,
	combout => \Add0~20_combout\,
	cout => \Add0~21\);

-- Location: FF_X49_Y42_N21
\time_count[10]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~20_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(10));

-- Location: LCCOMB_X49_Y42_N22
\Add0~22\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~22_combout\ = (time_count(11) & (!\Add0~21\)) # (!time_count(11) & ((\Add0~21\) # (GND)))
-- \Add0~23\ = CARRY((!\Add0~21\) # (!time_count(11)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(11),
	datad => VCC,
	cin => \Add0~21\,
	combout => \Add0~22_combout\,
	cout => \Add0~23\);

-- Location: FF_X49_Y42_N23
\time_count[11]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~22_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(11));

-- Location: LCCOMB_X49_Y42_N24
\Add0~24\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~24_combout\ = (time_count(12) & (\Add0~23\ $ (GND))) # (!time_count(12) & (!\Add0~23\ & VCC))
-- \Add0~25\ = CARRY((time_count(12) & !\Add0~23\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(12),
	datad => VCC,
	cin => \Add0~23\,
	combout => \Add0~24_combout\,
	cout => \Add0~25\);

-- Location: FF_X49_Y42_N25
\time_count[12]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~24_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(12));

-- Location: LCCOMB_X49_Y42_N26
\Add0~26\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~26_combout\ = (time_count(13) & (!\Add0~25\)) # (!time_count(13) & ((\Add0~25\) # (GND)))
-- \Add0~27\ = CARRY((!\Add0~25\) # (!time_count(13)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(13),
	datad => VCC,
	cin => \Add0~25\,
	combout => \Add0~26_combout\,
	cout => \Add0~27\);

-- Location: FF_X49_Y42_N29
\time_count[14]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~28_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(14));

-- Location: LCCOMB_X49_Y42_N28
\Add0~28\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~28_combout\ = (time_count(14) & (\Add0~27\ $ (GND))) # (!time_count(14) & (!\Add0~27\ & VCC))
-- \Add0~29\ = CARRY((time_count(14) & !\Add0~27\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100001100001100",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datab => time_count(14),
	datad => VCC,
	cin => \Add0~27\,
	combout => \Add0~28_combout\,
	cout => \Add0~29\);

-- Location: FF_X49_Y42_N31
\time_count[15]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~30_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(15));

-- Location: LCCOMB_X49_Y42_N30
\Add0~30\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~30_combout\ = \Add0~29\ $ (time_count(15))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111111110000",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	datad => time_count(15),
	cin => \Add0~29\,
	combout => \Add0~30_combout\);

-- Location: LCCOMB_X50_Y42_N10
\Equal0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~0_combout\ = (!\Add0~0_combout\ & (!\Add0~6_combout\ & (!\Add0~4_combout\ & !\Add0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~0_combout\,
	datab => \Add0~6_combout\,
	datac => \Add0~4_combout\,
	datad => \Add0~2_combout\,
	combout => \Equal0~0_combout\);

-- Location: LCCOMB_X50_Y42_N0
\Equal0~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~1_combout\ = (\Add0~8_combout\ & (!\Add0~12_combout\ & (!\Add0~10_combout\ & \Equal0~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~8_combout\,
	datab => \Add0~12_combout\,
	datac => \Add0~10_combout\,
	datad => \Equal0~0_combout\,
	combout => \Equal0~1_combout\);

-- Location: LCCOMB_X50_Y42_N2
\Equal0~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~2_combout\ = (\Add0~14_combout\ & (!\Add0~18_combout\ & (\Add0~16_combout\ & \Equal0~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~14_combout\,
	datab => \Add0~18_combout\,
	datac => \Add0~16_combout\,
	datad => \Equal0~1_combout\,
	combout => \Equal0~2_combout\);

-- Location: LCCOMB_X50_Y42_N24
\Equal0~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~3_combout\ = (!\Add0~24_combout\ & (!\Add0~22_combout\ & (!\Add0~20_combout\ & \Equal0~2_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~24_combout\,
	datab => \Add0~22_combout\,
	datac => \Add0~20_combout\,
	datad => \Equal0~2_combout\,
	combout => \Equal0~3_combout\);

-- Location: LCCOMB_X50_Y42_N6
\Equal0~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Equal0~4_combout\ = (!\Add0~26_combout\ & (!\Add0~28_combout\ & (!\Add0~30_combout\ & \Equal0~3_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~26_combout\,
	datab => \Add0~28_combout\,
	datac => \Add0~30_combout\,
	datad => \Equal0~3_combout\,
	combout => \Equal0~4_combout\);

-- Location: LCCOMB_X50_Y42_N28
\time_count~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \time_count~2_combout\ = (\Add0~8_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~8_combout\,
	datad => \Equal0~4_combout\,
	combout => \time_count~2_combout\);

-- Location: FF_X50_Y42_N29
\time_count[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \time_count~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(4));

-- Location: LCCOMB_X49_Y42_N10
\Add0~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~10_combout\ = (time_count(5) & (!\Add0~9\)) # (!time_count(5) & ((\Add0~9\) # (GND)))
-- \Add0~11\ = CARRY((!\Add0~9\) # (!time_count(5)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101101001011111",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(5),
	datad => VCC,
	cin => \Add0~9\,
	combout => \Add0~10_combout\,
	cout => \Add0~11\);

-- Location: FF_X49_Y42_N11
\time_count[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~10_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(5));

-- Location: LCCOMB_X49_Y42_N12
\Add0~12\ : cycloneiii_lcell_comb
-- Equation(s):
-- \Add0~12_combout\ = (time_count(6) & (\Add0~11\ $ (GND))) # (!time_count(6) & (!\Add0~11\ & VCC))
-- \Add0~13\ = CARRY((time_count(6) & !\Add0~11\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010010100001010",
	sum_lutc_input => "cin")
-- pragma translate_on
PORT MAP (
	dataa => time_count(6),
	datad => VCC,
	cin => \Add0~11\,
	combout => \Add0~12_combout\,
	cout => \Add0~13\);

-- Location: FF_X49_Y42_N13
\time_count[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \Add0~12_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(6));

-- Location: LCCOMB_X50_Y42_N20
\time_count~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \time_count~0_combout\ = (\Add0~14_combout\ & !\Equal0~4_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000010101010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \Add0~14_combout\,
	datad => \Equal0~4_combout\,
	combout => \time_count~0_combout\);

-- Location: FF_X50_Y42_N21
\time_count[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \time_count~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => time_count(7));

-- Location: LCCOMB_X48_Y42_N26
\LessThan1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan1~0_combout\ = ((!time_count(4) & (!time_count(5) & !time_count(3)))) # (!time_count(6))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100011111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(4),
	datab => time_count(5),
	datac => time_count(6),
	datad => time_count(3),
	combout => \LessThan1~0_combout\);

-- Location: LCCOMB_X48_Y42_N20
\LessThan2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan2~0_combout\ = (!time_count(10) & (!time_count(9) & (!time_count(11) & !time_count(12))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(10),
	datab => time_count(9),
	datac => time_count(11),
	datad => time_count(12),
	combout => \LessThan2~0_combout\);

-- Location: LCCOMB_X48_Y42_N18
\LessThan2~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan2~1_combout\ = (!time_count(13) & (!time_count(14) & (!time_count(15) & \LessThan2~0_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(13),
	datab => time_count(14),
	datac => time_count(15),
	datad => \LessThan2~0_combout\,
	combout => \LessThan2~1_combout\);

-- Location: LCCOMB_X48_Y42_N28
\LessThan1~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan1~1_combout\ = (!time_count(8) & (\LessThan2~1_combout\ & ((\LessThan1~0_combout\) # (!time_count(7)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(7),
	datab => time_count(8),
	datac => \LessThan1~0_combout\,
	datad => \LessThan2~1_combout\,
	combout => \LessThan1~1_combout\);

-- Location: LCCOMB_X48_Y42_N30
\always2~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~8_combout\ = (\LessThan1~1_combout\) # ((\always2~1_combout\ & \always2~0_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \always2~1_combout\,
	datac => \always2~0_combout\,
	datad => \LessThan1~1_combout\,
	combout => \always2~8_combout\);

-- Location: LCCOMB_X48_Y42_N6
\always2~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~5_combout\ = (time_count(4)) # ((time_count(2) & time_count(3)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101011110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(2),
	datac => time_count(4),
	datad => time_count(3),
	combout => \always2~5_combout\);

-- Location: LCCOMB_X48_Y42_N8
\always2~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~6_combout\ = (time_count(7)) # ((time_count(6)) # ((time_count(5) & \always2~5_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111111011111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(7),
	datab => time_count(5),
	datac => time_count(6),
	datad => \always2~5_combout\,
	combout => \always2~6_combout\);

-- Location: LCCOMB_X48_Y42_N14
\always2~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~7_combout\ = (!\always2~0_combout\ & (((time_count(8) & \always2~6_combout\)) # (!\LessThan2~1_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0010000000110011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(8),
	datab => \always2~0_combout\,
	datac => \always2~6_combout\,
	datad => \LessThan2~1_combout\,
	combout => \always2~7_combout\);

-- Location: LCCOMB_X48_Y42_N22
\LessThan2~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan2~3_combout\ = ((!time_count(3) & (!time_count(4) & !time_count(2)))) # (!time_count(5))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100110111",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => time_count(3),
	datab => time_count(5),
	datac => time_count(4),
	datad => time_count(2),
	combout => \LessThan2~3_combout\);

-- Location: IOIBUF_X45_Y43_N1
\datain[5]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(5),
	o => \datain[5]~input_o\);

-- Location: LCCOMB_X45_Y42_N6
\B~10\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~10_combout\ = (!\clr~input_o\ & \datain[5]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[5]~input_o\,
	combout => \B~10_combout\);

-- Location: FF_X45_Y42_N7
\B[5]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~10_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(5));

-- Location: IOIBUF_X45_Y43_N29
\datain[6]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(6),
	o => \datain[6]~input_o\);

-- Location: LCCOMB_X45_Y42_N20
\B~11\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~11_combout\ = (!\clr~input_o\ & \datain[6]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[6]~input_o\,
	combout => \B~11_combout\);

-- Location: FF_X45_Y42_N21
\B[6]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~11_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(6));

-- Location: IOIBUF_X50_Y43_N15
\datain[7]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(7),
	o => \datain[7]~input_o\);

-- Location: LCCOMB_X45_Y42_N22
\B~12\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~12_combout\ = (!\clr~input_o\ & \datain[7]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[7]~input_o\,
	combout => \B~12_combout\);

-- Location: FF_X45_Y42_N23
\B[7]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~12_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(7));

-- Location: IOIBUF_X41_Y43_N1
\datain[4]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(4),
	o => \datain[4]~input_o\);

-- Location: LCCOMB_X45_Y42_N12
\B~9\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~9_combout\ = (!\clr~input_o\ & \datain[4]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[4]~input_o\,
	combout => \B~9_combout\);

-- Location: FF_X45_Y42_N13
\B[4]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~9_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(4));

-- Location: LCCOMB_X45_Y42_N28
\always2~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~2_combout\ = (!B(5) & (!B(6) & (!B(7) & !B(4))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000000001",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(5),
	datab => B(6),
	datac => B(7),
	datad => B(4),
	combout => \always2~2_combout\);

-- Location: LCCOMB_X45_Y42_N14
\always2~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~3_combout\ = (\always2~1_combout\ & (\always2~0_combout\ & \always2~2_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010000000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \always2~1_combout\,
	datac => \always2~0_combout\,
	datad => \always2~2_combout\,
	combout => \always2~3_combout\);

-- Location: LCCOMB_X48_Y42_N12
\LessThan2~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \LessThan2~2_combout\ = (!time_count(8) & (!time_count(7) & \LessThan2~1_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000001100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => time_count(8),
	datac => time_count(7),
	datad => \LessThan2~1_combout\,
	combout => \LessThan2~2_combout\);

-- Location: LCCOMB_X48_Y42_N24
\always2~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \always2~4_combout\ = (\always2~3_combout\) # ((\LessThan2~2_combout\ & ((\LessThan2~3_combout\) # (!time_count(6)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101111110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \LessThan2~3_combout\,
	datab => time_count(6),
	datac => \always2~3_combout\,
	datad => \LessThan2~2_combout\,
	combout => \always2~4_combout\);

-- Location: LCCOMB_X48_Y42_N16
\en~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \en~0_combout\ = (\always2~8_combout\ & (!\always2~7_combout\ & \always2~4_combout\))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110000000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \always2~8_combout\,
	datac => \always2~7_combout\,
	datad => \always2~4_combout\,
	combout => \en~0_combout\);

-- Location: FF_X48_Y42_N17
\en[0]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \en~0_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \en[0]~reg0_q\);

-- Location: LCCOMB_X48_Y42_N4
\en[1]~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \en[1]~1_combout\ = (!\always2~7_combout\ & ((\LessThan1~1_combout\) # ((\always2~1_combout\ & \always2~0_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \always2~1_combout\,
	datab => \always2~0_combout\,
	datac => \always2~7_combout\,
	datad => \LessThan1~1_combout\,
	combout => \en[1]~1_combout\);

-- Location: LCCOMB_X48_Y42_N2
\en~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \en~2_combout\ = (!\always2~4_combout\ & \en[1]~1_combout\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011000000110000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \always2~4_combout\,
	datac => \en[1]~1_combout\,
	combout => \en~2_combout\);

-- Location: FF_X48_Y42_N3
\en[1]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \en~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \en[1]~reg0_q\);

-- Location: LCCOMB_X48_Y42_N0
\en~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \en~3_combout\ = (!\always2~7_combout\ & (!\LessThan1~1_combout\ & ((!\always2~0_combout\) # (!\always2~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000000000010011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \always2~1_combout\,
	datab => \always2~7_combout\,
	datac => \always2~0_combout\,
	datad => \LessThan1~1_combout\,
	combout => \en~3_combout\);

-- Location: FF_X48_Y42_N1
\en[2]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \en~3_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \en[2]~reg0_q\);

-- Location: FF_X48_Y42_N15
\en[3]~reg0\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \always2~7_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => \en[3]~reg0_q\);

-- Location: IOIBUF_X41_Y43_N15
\datain[1]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(1),
	o => \datain[1]~input_o\);

-- Location: LCCOMB_X44_Y42_N14
\B~14\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~14_combout\ = (!\clr~input_o\ & \datain[1]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[1]~input_o\,
	combout => \B~14_combout\);

-- Location: FF_X44_Y42_N15
\B[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~14_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(1));

-- Location: LCCOMB_X48_Y42_N10
\data[3]~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data[3]~0_combout\ = (!\always2~7_combout\ & ((\always2~4_combout\) # (!\always2~8_combout\)))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0011001100000011",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datab => \always2~7_combout\,
	datac => \always2~8_combout\,
	datad => \always2~4_combout\,
	combout => \data[3]~0_combout\);

-- Location: LCCOMB_X44_Y42_N16
\data~3\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~3_combout\ = (\data[3]~0_combout\ & (((\en[1]~1_combout\)))) # (!\data[3]~0_combout\ & ((\en[1]~1_combout\ & (B(5))) # (!\en[1]~1_combout\ & ((B(13))))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111101000001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(5),
	datab => B(13),
	datac => \data[3]~0_combout\,
	datad => \en[1]~1_combout\,
	combout => \data~3_combout\);

-- Location: LCCOMB_X44_Y42_N22
\data~4\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~4_combout\ = (\data[3]~0_combout\ & ((\data~3_combout\ & ((B(1)))) # (!\data~3_combout\ & (B(9))))) # (!\data[3]~0_combout\ & (((\data~3_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(9),
	datab => B(1),
	datac => \data[3]~0_combout\,
	datad => \data~3_combout\,
	combout => \data~4_combout\);

-- Location: FF_X44_Y42_N23
\data[1]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \data~4_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(1));

-- Location: IOIBUF_X43_Y43_N8
\datain[0]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(0),
	o => \datain[0]~input_o\);

-- Location: LCCOMB_X44_Y42_N30
\B~13\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~13_combout\ = (!\clr~input_o\ & \datain[0]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[0]~input_o\,
	combout => \B~13_combout\);

-- Location: FF_X44_Y42_N31
\B[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~13_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(0));

-- Location: LCCOMB_X44_Y42_N0
\data~1\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~1_combout\ = (\data[3]~0_combout\ & (((\en[1]~1_combout\)))) # (!\data[3]~0_combout\ & ((\en[1]~1_combout\ & ((B(4)))) # (!\en[1]~1_combout\ & (B(12)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(12),
	datab => B(4),
	datac => \data[3]~0_combout\,
	datad => \en[1]~1_combout\,
	combout => \data~1_combout\);

-- Location: LCCOMB_X44_Y42_N12
\data~2\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~2_combout\ = (\data[3]~0_combout\ & ((\data~1_combout\ & (B(0))) # (!\data~1_combout\ & ((B(8)))))) # (!\data[3]~0_combout\ & (((\data~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1010111111000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(0),
	datab => B(8),
	datac => \data[3]~0_combout\,
	datad => \data~1_combout\,
	combout => \data~2_combout\);

-- Location: FF_X44_Y42_N13
\data[0]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \data~2_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(0));

-- Location: IOIBUF_X43_Y43_N29
\datain[3]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(3),
	o => \datain[3]~input_o\);

-- Location: LCCOMB_X44_Y42_N26
\B~16\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~16_combout\ = (!\clr~input_o\ & \datain[3]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0101000001010000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \clr~input_o\,
	datac => \datain[3]~input_o\,
	combout => \B~16_combout\);

-- Location: FF_X44_Y42_N27
\B[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~16_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(3));

-- Location: LCCOMB_X44_Y42_N28
\data~7\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~7_combout\ = (\data[3]~0_combout\ & ((B(11)) # ((\en[1]~1_combout\)))) # (!\data[3]~0_combout\ & (((B(15) & !\en[1]~1_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111000010101100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(11),
	datab => B(15),
	datac => \data[3]~0_combout\,
	datad => \en[1]~1_combout\,
	combout => \data~7_combout\);

-- Location: LCCOMB_X44_Y42_N20
\data~8\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~8_combout\ = (\en[1]~1_combout\ & ((\data~7_combout\ & ((B(3)))) # (!\data~7_combout\ & (B(7))))) # (!\en[1]~1_combout\ & (((\data~7_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111010110001000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => \en[1]~1_combout\,
	datab => B(7),
	datac => B(3),
	datad => \data~7_combout\,
	combout => \data~8_combout\);

-- Location: FF_X44_Y42_N21
\data[3]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \data~8_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(3));

-- Location: IOIBUF_X50_Y43_N29
\datain[2]~input\ : cycloneiii_io_ibuf
-- pragma translate_off
GENERIC MAP (
	bus_hold => "false",
	simulate_z_as => "z")
-- pragma translate_on
PORT MAP (
	i => ww_datain(2),
	o => \datain[2]~input_o\);

-- Location: LCCOMB_X45_Y42_N26
\B~15\ : cycloneiii_lcell_comb
-- Equation(s):
-- \B~15_combout\ = (!\clr~input_o\ & \datain[2]~input_o\)

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000111100000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	datac => \clr~input_o\,
	datad => \datain[2]~input_o\,
	combout => \B~15_combout\);

-- Location: FF_X45_Y42_N27
\B[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \B~15_combout\,
	ena => \B[2]~1_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => B(2));

-- Location: LCCOMB_X45_Y42_N0
\data~5\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~5_combout\ = (\data[3]~0_combout\ & (((\en[1]~1_combout\)))) # (!\data[3]~0_combout\ & ((\en[1]~1_combout\ & ((B(6)))) # (!\en[1]~1_combout\ & (B(14)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1111110000001010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(14),
	datab => B(6),
	datac => \data[3]~0_combout\,
	datad => \en[1]~1_combout\,
	combout => \data~5_combout\);

-- Location: LCCOMB_X45_Y42_N8
\data~6\ : cycloneiii_lcell_comb
-- Equation(s):
-- \data~6_combout\ = (\data[3]~0_combout\ & ((\data~5_combout\ & ((B(2)))) # (!\data~5_combout\ & (B(10))))) # (!\data[3]~0_combout\ & (((\data~5_combout\))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1100111110100000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => B(10),
	datab => B(2),
	datac => \data[3]~0_combout\,
	datad => \data~5_combout\,
	combout => \data~6_combout\);

-- Location: FF_X45_Y42_N9
\data[2]\ : dffeas
-- pragma translate_off
GENERIC MAP (
	is_wysiwyg => "true",
	power_up => "low")
-- pragma translate_on
PORT MAP (
	clk => \clk~inputclkctrl_outclk\,
	d => \data~6_combout\,
	devclrn => ww_devclrn,
	devpor => ww_devpor,
	q => data(2));

-- Location: LCCOMB_X41_Y42_N28
\WideOr6~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr6~0_combout\ = (data(3) & (data(0) & (data(1) $ (data(2))))) # (!data(3) & (!data(1) & (data(0) $ (data(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100000110000100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr6~0_combout\);

-- Location: LCCOMB_X41_Y42_N10
\WideOr5~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr5~0_combout\ = (data(1) & ((data(0) & (data(3))) # (!data(0) & ((data(2)))))) # (!data(1) & (data(2) & (data(0) $ (data(3)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011011010000000",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr5~0_combout\);

-- Location: LCCOMB_X41_Y42_N4
\WideOr4~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr4~0_combout\ = (data(3) & (data(2) & ((data(1)) # (!data(0))))) # (!data(3) & (data(1) & (!data(0) & !data(2))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1011000000000010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr4~0_combout\);

-- Location: LCCOMB_X41_Y42_N26
\WideOr3~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr3~0_combout\ = (data(1) & ((data(0) & ((data(2)))) # (!data(0) & (data(3) & !data(2))))) # (!data(1) & (!data(3) & (data(0) $ (data(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1000100100100100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr3~0_combout\);

-- Location: LCCOMB_X41_Y42_N12
\WideOr2~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr2~0_combout\ = (data(1) & (data(0) & (!data(3)))) # (!data(1) & ((data(2) & ((!data(3)))) # (!data(2) & (data(0)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0000110101001100",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr2~0_combout\);

-- Location: LCCOMB_X41_Y42_N18
\WideOr1~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr1~0_combout\ = (data(1) & (!data(3) & ((data(0)) # (!data(2))))) # (!data(1) & (data(0) & (data(3) $ (!data(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "0100100000001110",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr1~0_combout\);

-- Location: LCCOMB_X41_Y42_N8
\WideOr0~0\ : cycloneiii_lcell_comb
-- Equation(s):
-- \WideOr0~0_combout\ = (data(0) & ((data(3)) # (data(1) $ (data(2))))) # (!data(0) & ((data(1)) # (data(3) $ (data(2)))))

-- pragma translate_off
GENERIC MAP (
	lut_mask => "1110011111111010",
	sum_lutc_input => "datac")
-- pragma translate_on
PORT MAP (
	dataa => data(1),
	datab => data(0),
	datac => data(3),
	datad => data(2),
	combout => \WideOr0~0_combout\);

ww_en(0) <= \en[0]~output_o\;

ww_en(1) <= \en[1]~output_o\;

ww_en(2) <= \en[2]~output_o\;

ww_en(3) <= \en[3]~output_o\;

ww_codeout(0) <= \codeout[0]~output_o\;

ww_codeout(1) <= \codeout[1]~output_o\;

ww_codeout(2) <= \codeout[2]~output_o\;

ww_codeout(3) <= \codeout[3]~output_o\;

ww_codeout(4) <= \codeout[4]~output_o\;

ww_codeout(5) <= \codeout[5]~output_o\;

ww_codeout(6) <= \codeout[6]~output_o\;

ww_codeout(7) <= \codeout[7]~output_o\;
END structure;


